ATM networks are essentially asynchronous in nature. In some applications, some means of recovering timing information as the data is transported through the network must be provided. For example, when a TDM link, such as a primary rate link, is connected to the output of an ATM switch, the timing information must be recovered to generate the primary rate clock of the source link.
One known method of recovering timing information across ATM networks is the Synchronous Residual Time Stamp (SRTS). This process, which assumes the network is timed to a master clock, is defined in ITU Recommendation I.363. The ATM network clock is taken and divided by 2[k], where k=0.1 . . . 11. k is chosen to produce a frequency near the service bit-rate of the source link (greater than but less than twice the rate). The difference between the service bit-rate and the network related frequency is produced and the 4 LSBs of this difference are transmitted using 4 CSI bits from 8 successive ATM cells. These 4 bits comprise the SRTS. Both transmitter and receiver carry out this process and by comparing the locally produced SRTS with the received far-end SRTS, the local clock can be synchronized to the remote clock. Section 6 of the Bellcore document, GR-1113-CORE describes in detail a method of implementing STRS clock recovery.
In a known method of primary rate clock recovery (See Integrated Telecom Technology, Inc. AAL1 SAR Processor WAC-021_B, User's Manual, Data Sheet, 1996) the 1.544 MHz nominal primary rate clock is recovered using the Synchronous Residual Time Stamp (SRTS) method. The SRTS value transported over the ATM fabric is extracted by the SAR device at the receiver. This device compares the received SRTS value with a locally generated SRTS value derived from the receiver clock and outputs a signed 4-bit correction value having a value between -8 and +7.
The correction value is used to control the number of pulses of a 1.55520 MHz clock to be multiplexed with a fixed number of 1.495384 MHz clock pulses. The suggested ratio is 158+n 1.5552 MHz pulses to 35 1.495384 MHz pulses in a period of 193+n pulses, where n=the SRTS correction value. Thus, if the correction value is zero (signifying a nominal 1.544 MHz clock), the output clock will have a frequency deviation (fd) from nominal of +11,200/-48,616 Hz. The frequency of modulation from nominal fm) depends on the implementation with a non-sinusoidal 8 kHz fm at the low end, which will vary slightly depending on the magnitude and sign of the correction value. This represents intrinsic jitter, which can be defined in peak-peak Unit Intervals (UI) as Jp-p=fd/.pi.*fm, where fm is a sinusoidal modulating frequency and fd is the frequency of deviation of the carrier frequency.
The use of a correction value implies that the output clock is averaged over time to arrive at the final locked frequency. This function creates low frequency jitter. Any averaging jitter below 6 Hz (more properly referred to as wander) will pass through the jitter attenuator unattenuated. The SRTS method itself also has the characteristic of waiting time jitter, which, by nature, is 1 UI. The above prior art arrangement is relatively complicated to implement.
The prior art method of clock recovery requires complex logic circuitry to implement.
An object of the invention is to provide a clock recovery method that can be implemented with simple logic circuitry.